Anders Jørgensen
FPGA Engineer
About
FPGA Engineer with 7+ Years of Industry Experience. 33-year-old independent FPGA engineer, proficient at high-speed communication and low-latency designs, capable of taking concepts from idea to fully functional production.
Work Experience
December 2023 – Present
FPGA Engineer - Alipes Capital
Implementing low latency RTL designs used in the financial industry.
April 2018 – November 2023
FPGA/ASIC Design Engineer - Zeuxion Aps
Implementing high speed RTL designs used in the telecommunication industry.
January 2014 – February 2018
IT student assistant - Det Danske Sprog- og Litteraturselskab
Maintaining the server farm and General IT support
Highlights
- Server management using Saltstack
- Maintaining network and virtualisation (Xenserver) environment
- Buying new server equipment
- Converting existing service to a container-based(Docker) environment.
Education
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2016 2018
Technical University of Denmark
University
M.Sc. Telecommunications
-
2012 2015
Technical University of Denmark
University
B.Sc. IT and Network technology
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2012 2009
Selandia Slagelse
High school
HTX
-
1999 2009
Høng Privat Skole
Primary school
Primary School
Skills
FPGA development
RTL design
Packet switching
DMA Modelsim/Questasim
VCS
PCIe DDR4
Xilinx Ultrascale+
Xilinx Versal Xilinx Vivado
Xilinx SDK/Vitis Xilinx HBM
Quartus Intel Stratix 10
Intel Agilex
Transceiver Xilinx/Intel Timing closure
Pin layout Floorplanning
Network
OSI model
Ethernet
OTN FlexE
IPv6
IPv4 TCP
UDP
DNS DHCP
PTP 1588
QUIC Zigbee
System
Docker
SaltStack
ZFS Linux
AWS
Digitalocean Xenserver
Git/SVN
CI/CD Ubuntu
Jenkins
Teamcity Proxmox
Finacial
FIX protocol
Langages
System Verilog
Verilog
VHDL Python
TCL
Bash
Interests
Network and IT infrastructure
IoT, arduino/esp8266 - Smarthome, Home assistant
Lego
Motorsport/Simracing